An Eecient Vlsi Architecture for Columnsort

| This paper presents novel VLSI architecture in support of an eecient implementation of Leighton's well-known Columnsort. The designs take advantage of re-conngurable bus architectures enhanced with simple shift switches. Our main contribution is to show that (1) Column-sort can be partitioned into two components of hardware scheme involving sorting arrays of small size and a hardware or software scheme involving simple data movement tasks, (2) The dynamically reconngurable mesh architecture can be exploited to obtain a highly eecient small hardware sorter. The proposed architecture features high regularity of circuitry, simplicity of control structure, and adaptability. Both theoretical analyses and simulation tests have shown that the proposed VLSI architecture for sorting are superior to the existing designs in the context of sorting small and moderate size arrays.